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I am an Assistant Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology (ISM) Dhanbad. Prior to joining IIT (ISM), I served as an Assistant Professor at the National Institute of Technology Tiruchirappalli and KIIT Deemed to be University. I received my Ph.D. from the Department of Computer Science and Engineering at the Indian Institute of Technology Guwahati. I hold an M.Tech. degree in Computer Science and Engineering from Veer Surendra Sai University of Technology (VSSUT), Burla.​​

Academic

  • PhD: Department of CSE, Indian Institute of Technology Guwahati, 2024

  • MTech: Dept. of CSE, Veer Surendra Sai University of Technology (VSSUT) Burla, Odisha, 2015

  • BTech: Dept. of CSE, Roland Institute of Technology, BPUT, Odisha, 2012​

About: Academic

Experience

  • Assistant Professor, Department of CSE, IIT(ISM) Dhanbad, Jharkhand, May 2026 - Present

  • Assistant Professor, Department of CSE, NIT Trichy, Tamil Nadu, Dec 2025 - May 2026

  • Assistant Professor, School of Computer Science, KIIT, Bhubaneswar, Odisha, July 2024 - Dec 2025​

  • Lecturer, Department of IT, CET, Bhubaneswar, Odisha, June 2016 - June 2017​

  • Lecturer, Department of CSE, VSSUT, Burla, Odisha, Aug 2015 - May 2016

About: Experience

Teaching

Assistant Professor at NIT Trichy

  • Compiler Design (CSPC62) — Even Sem, 2025–26

  • Introduction to Computer Programming (CSIR12) — Even Sem, 2025–26

Assistant Professor at KIIT Deemed to be University

  • Automata Theory and Formal Languages (CS21003) — Odd Sem, 2025–26

  • Database Management Systems (CS20006) — Even Sem, 2024–25

  • Database Management Systems Laboratory (CS29006) — Even Sem, 2024–25

  • Artificial Intelligence (CS30002) — Even Sem, 2024–25

  • Design and Analysis of Algorithms (CS30001) — Odd Sem, 2024–25

  • Computer Networks (CS30003) — Odd Sem, 2024–25

  • Design and Analysis of Algorithms Laboratory (CS39001) — Odd Sem, 2024–25

  • Computer Networks Laboratory (CS39003) — Odd Sem, 2024–25

Teaching Assistant at IIT Guwahati

  • NPTEL Course on C Based VLSI Design: July-Oct 2021, July-Oct 2022, July-Oct 2023

  • CS221: Digital Design

  • CS322M: Digital Logic and Computer Architecture

  • CS 577: C-Based VLSI Design: Synthesis, Optimization and Verification

  • CS593: Data Structures and Databases Lab

  • CS110: Introduction to Computing Lab

  • CS210: Data Structure Lab

  • CS513: Programming Lab

About: Experience
Teaching
Research
Research

Research Interest: compiler systems, software security, program analysis, formal verification, and secure compiler optimizations. My current research focuses on developing methods to verify the security preservation of compiler optimizations using static analysis, bisimulation, and model-checking techniques.

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Ph.D. Thesis: Security Verification of Compiler Optimizations: An Information Flow  Perspective

Supervisor: Dr. Chandan Karfa, Associate Professor, IIT Guwahati, Assam

Publications

Journals

  • Priyanka Panigrahi, and Chandan Karfa, “MQIL: Model Checking based Quantification of Information Leakage,”in IEEE Embedded Systems Letters (ESL), Mar. 2026, doi: 10.1109/LES.2026.3677498, Q2, IF:2.

  • Priyanka Panigrahi, and Chandan Karfa, “Translation Validation of Information Leakage of Compiler Optimizations”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 11, pp. 3585-3598, Nov. 2023, doi: 10.1109/TCAD.2023.3269954, Q1, IF: 2.9.

  • Priyanka Panigrahi, Abhik Paul and Chandan Karfa, “Quantifying Information Leakage for Security Verification of Compiler Optimizations,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 11, pp. 4385-4396, Nov. 2022, doi: 10.1109/TCAD.2022.3200914, Q1, IF: 2.9.

  • Priyanka Panigrahi, Vemuri Sahithya, Chandan Karfa, and Prabhat Mishra, “Secure Register Allocation for Trusted Code Generation,” in IEEE Embedded Systems Letters (ESL), vol. 14, no. 3, pp. 127-130, Sept. 2022, doi: 10.1109/LES.2022.3151096, Q2, IF: 2.

Conferences

  • Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha, and Chandan Karfa, “SRIL: Securing Registers from Information Leakage at Register Transfer Level”, in 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems (VLSID), Kolkata, India, 2024, pp. 492-498, doi:10.1109/VLSID60093.2024.00088.

  • Priyanka Panigrahi and Chandan Karfa, “An Investigation into the Security of Register Allocation with Spillin and Splitting”, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Foz do Iguacu, Brazil, 2023, pp 1-6, doi: 10.1109/ISVLSI59464.2023.10238662.

  • Priyanka Panigrahi, Rajesh Kumar Jha, and Chandan Karfa, (2019). “User Guided Register Manipulation in Digita Circuits”, in VLSI Design and Test (VDAT), 2019, pp. 468–481, Communications in Computer and Information Science, vol 1066. Springer, Singapore, https://doi.org/10.1007/978-981-32-9767-8_39.

About: Publications
Achivements

  • Fellowship for attending VLSID 2024

  • Ph.D Thesis accepted in the Ph.D. Forum of VLSID 2024

  • Winner of the Qualcomm Innovation Fellowship (QIF), India, 2022

  • Ph.D. Thesis accepted in the Ph.D. Forum of IEEE WINTECHCON 2022

  • Finalist of the Qualcomm Innovation Fellowship (QIF), India, 2021

  • Travel Grant for attending VDAT 2019

  • GATE Fellowship for Ph.D. awarded by MHRD, Government of India (2017–2022)

  • GATE Fellowship for M.Tech. awarded by MHRD, Government of India (2013–2015)

  • Qualified GATE in 2011 and 2012

  • Branch Topper in the 2nd, 3rd, and 4th semesters of B.Tech.

Achivements

Extracurricular

  • Attended the AICTE Training and Learning (ATAL) Academy Faculty Development Program on “Optimizing Next-Gen Computing for Smart System Development”, National Institute of Technology Warangal, 13–18 October 2025.

  • Attended the KIIT Academic Empowerment Program on “The Evolving Role of Faculty in Higher Education Institutions: Beyond the Classroom”, KIIT Deemed to be University, Bhubaneswar, Odisha, 20–26 June 2025.

  • Presented the paper “SRIL: Securing Registers from Information Leakage at Register Transfer Level” at the VLSID 2024.

  • Presented the paper “User-Guided Register Manipulation in Digital Circuits” at the VDAT 2019.

  • Attended the Workshop on Advances in Hardware Security, IIT Guwahati, 24–29 May 2019.

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